1. Field of the Invention
The present invention relates to a semiconductor storage device.
2. Description of the Related Art
Conventionally, there is a half VDD (HVDD) precharge scheme adopting a voltage ½ of a power supply potential VDD as a precharge voltage of a bit line. FIG. 7 shows a circuit configuration of DRAM (Dynamic Random Access Memory) based on a general HVDD precharge scheme. As shown in FIG. 7, a DRAM circuit 1 has a memory cell 2, a precharge circuit 3, a sense amplifier 4, an HVDD power supply 5 and a bit line pair D, DB. The HVDD power supply 5 that supplies a potential ½ of the power supply potential VDD (hereinafter described as “½ VDD”) is connected to the precharge circuit 3. The precharge circuit 3 precharges the bit line pair D, DB to ½ VDD during a precharge operation. Suppose this ½ VDD is a reference voltage.
Operations of the DRAM circuit 1 will be explained briefly using FIG. 8. In this example, suppose high level data is stored in the memory cell 2. For convenience' sake, suppose symbols “WL0,” “SE” and “PDL” denote their respective wiring names and at the same time denote signal names outputted to the wirings. Suppose the same will apply to other wirings hereinafter.
First, before time t1, a word line signal WL0, a sense amplifier control signal SE and a precharge control signal PDL are at low levels respectively. Therefore, a memory cell transistor TrO of the memory cell 2 is OFF and operations of the sense amplifier 4 and precharge circuit 5 are stopped. Furthermore, a bit line pair DO, DBO has already been equalized and precharged and their respective potentials are set to ½ VDD.
At time t1, the word line signal WLO is driven high. This causes the memory cell transistor TrO to turn ON and causes the charge of a memory cell capacitor C0 to be transmitted to the bit line DO. The potential of the bit line DO then slightly rises above the reference voltage. A voltage VPP, which is higher than the power supply voltage VDD, is supplied as the potential of the word line signal WLO in this case. This is intended to ensure that the memory cell transistor TrO is held in an ON state.
At time t2, the sense amplifier control signal SE is driven high and the sense amplifier 4 operates. This causes the potential difference between the bit line pair DO, DBO to be amplified. This potential difference is read by an external circuit and becomes output data of the DRAM circuit 1.
At time t3, the word line signal WLO is driven low and the precharge control signal PDL is driven high. This causes the memory cell transistor TrO to turn OFF and causes the precharge circuit 3 to start a precharge operation.
At time t4, the precharge operation of the precharge circuit 3 causes the bit line pair DO, DBO to be equalized and precharged and their respective potentials become ½ VDD.
However, the DRAM circuit 1 based on such an HVDD precharge scheme has the following problems. First, the cell capacitor C0 is connected to one of the drain and the source of the cell transistor TrO. Therefore, when high level data is held in the memory cell, the charged charge of the cell capacitor C0 leaks out on a back bias (normally, grounding potential) side of the cell transistor TrO. Therefore, when the memory cell transistor TrO turns ON, a potential rise from ½ VDD of the bit line DO becomes smaller by the amount of leaked charge. With circuit miniaturization in recent years, this problem is becoming increasingly noticeable. On the contrary, when low level data is held in the memory cell, the above described leakage of charge does not occur, and therefore there is no problem with data holding characteristics. That is, the margin of the data holding characteristics of the memory cell depends on the degree of rise of the potential of the bit line from the reference voltage when high level data is read. This margin is increased by lowering the reference voltage.
Next, miniaturization of manufacturing processes causes the gate breakdown voltage of the memory cell transistor TrO to decrease. This prevents the potential of the voltage VPP from increasing when the word line signal WLO is driven high. This results in insufficient writing of the high level potential to the cell capacitor CO when high level data is written to the memory cell 2.
Furthermore, during operation of the sense amplifier 4, both the PMOS transistor and NMOS transistor making up the sense amplifier 4 are given only ½ VDD as their gate voltages. Therefore, when the power supply voltage VDD drops, it approximates to a threshold voltage of the transistor, causing the operating voltage of the sense amplifier 4 to become insufficient. This makes it difficult for the sense amplifier 4 to operate. This constitutes a disadvantage to a power supply voltage which tends to decrease in recent years.
To cope with such a problem, scheme for making the reference voltage lower than ½ VDD are being developed. Lowering the reference voltage allows a margin of data holding characteristics of the memory cell to increase when holding high level data. One example of such a technique is the technique described in Japanese Patent Laid-Open No. 8-297974. FIG. 9 shows a configuration of a semiconductor storage device 10 of Japanese Patent Laid-Open No. 8-297974. As shown in FIG. 9, a semiconductor storage device 10 has precharge circuits 21 to 24, memory cells 31 to 34 and sense amplifiers 41 to 44. A precharge control signal VBP is inputted to the precharge circuits 21 to 24 respectively. A word line signal WLO is inputted to the memory cells 31 to 34 respectively. A sense amplifier control signal SE is inputted to the sense amplifiers 41 to 44 respectively. The precharge circuit 21, memory cell 31 and sense amplifier 41 are each connected to a bit line pair D1, DB1. The precharge circuits 22 to 24, memory cells 32 to 34 and sense amplifiers 42 to 44 are likewise connected to bit line pairs D2, DB2 to D4, DB4 respectively. However, only the precharge circuit 21 has a pull-down circuit 51. The pull-down circuit 51 has NMOS transistors Tr11 and Tr12. The NMOS transistors Tr11 and Tr12 are connected between the bit line pair D1 and a grounding voltage GND and between DB1 and the grounding voltage GND respectively. ON/OFF of the NMOS transistors Tr11 and Tr12 is controlled by an equalizing control signal VEQ inputted to their gates.
Operations of the semiconductor storage device 10 will be explained briefly using FIG. 10. In this example, suppose high level data is held in a memory cell capacitor C11. At time t1, the precharge control signal VBP is driven low. By this time, the respective bit line pairs D1, DB1 to D4, DB4 have been precharged to a voltage VBL.
During time t2 to t4, the word line signal WLO is held high. This causes the data held in the memory cells 31 to 34 to be read to the bit line pairs D1, DB1 to D4, DB4. During time t3 to t5, the sense amplifier control signal SE is held high, which causes the sense amplifiers 41 to 44 to operate. The sense amplifiers 41 to 44 amplify the data read to the respective bit lines. Of the read data, data of a selected bit line pair is read to an external circuit and becomes output data of the semiconductor storage device 10.
During time t6 to t7 (period TEQG), the equalizing control signal VEQ is held high. This causes the potential of the bit line pair D1, DB1 to become a grounding potential GND. At time t8, the precharge control signal VBP is driven high. This causes precharging and equalizing to be performed. The precharging and equalizing operations cause all bit line pairs D1, DB1 to D4, DB4, that is, a total of eight bit lines to be connected via the precharge control signal line and cause charge to be shared. As a result, since the bit line pair D1, DB1 is discharged, the potentials of eight bit lines become ⅜ VDD, which is lower than ½ VDD. Using this ⅜ VDD as a reference voltage avoids the above described problem.
In order to cause the reference voltage to fall below ½ VDD, the semiconductor storage device 10 of Japanese Patent Laid-Open No. 8-297974 connects the bit line pair D1, DB1 to the grounding potential GND so as to produce a discharge. This requires a period TEQG in FIG. 10 in addition to a one-cycle operation of normal read/write and provides a disadvantage in making the semiconductor storage device operate faster.